Why does my PLL fail to lock even though PLLM, PLLN, PLLP, and PLLQ all look like reasonable numbers?

Check the VCO output frequency, not just the individual register fields. f_vco_out = (f_source / PLLM) × PLLN must land between 100 MHz and 432 MHz on F4/F7-style parts. It's easy to pick a PLLM/PLLN pair where each field is individually within its own valid range (PLLM 2-63, PLLN 50-432) but the resulting VCO output is outside 100-432 MHz. The reference manual doesn't stop you from writing an out-of-range VCO configuration; the PLL just won't behave.

My USB device doesn't enumerate even though SYSCLK is correct. What's wrong?

USB OTG FS, SDIO, and RNG all clock off PLLQ, a separate divider from PLLP that taps the same VCO output. Check f_usb = f_vco_out / PLLQ. It needs to equal 48 MHz exactly, not approximately. Some SYSCLK targets (180 MHz on F42x/43x is a common one, since its 360 MHz VCO output has no integer PLLQ landing on 48 MHz) can't reach exact 48 MHz from the main PLL at all. Those parts route USB through PLLSAI, a second independent PLL, instead.

Should I always aim for a 2 MHz VCO input frequency?

It's the RM0090/RM0410-recommended value because it minimizes PLL jitter, and it's achievable for most common HSE crystals (8, 12, 16 MHz all divide evenly to 2 MHz). A 25 MHz crystal can't reach exactly 2 MHz with an integer PLLM, so designs using it typically land on 1 MHz instead (PLLM = 25), which is still inside the valid 1-2 MHz range, just not the jitter-optimal value. Both are legal; 2 MHz is simply the better choice when your crystal allows it.

Does this calculator apply to STM32L4, G4, or H7?

Only loosely. L4 and G4 share the same M/N/P/Q concept but use different numeric ranges for the VCO input/output and PLLM, plus an extra PLLR divider this calculator doesn't model. H7 uses a substantially different register layout with separate pre/post dividers per PLL and fractional-N support. This calculator models the classic single-main-PLL PLLCFGR topology used on F4 and F7 specifically. Check the RCC chapter of your part's reference manual before reusing these numbers on a different family.

STM32 PLL / Clock Tree Calculator

HSE	M	N	P	Q	Target	SYSCLK	USB
8 MHz	4	168	2	7	F405/407 (168 MHz)	168 MHz	48 MHz
12 MHz	6	168	2	7	F405/407 (168 MHz)	168 MHz	48 MHz
16 MHz	8	168	2	7	F405/407 (168 MHz)	168 MHz	48 MHz
25 MHz	25	336	2	7	F405/407 (168 MHz)	168 MHz	48 MHz
8 MHz	4	180	2	7	F42x/43x (180 MHz)	180 MHz	51.4286 MHz
8 MHz	4	216	2	9	F7 series (216 MHz)	216 MHz	48 MHz

What PLLCFGR actually controls

STM32F4 and F7 parts derive SYSCLK from a single main PLL fed by RCC_PLLCFGR: four fields, four dividers/multipliers, one register.

f_vco_in  = f_pll_source / PLLM
f_vco_out = f_vco_in × PLLN
SYSCLK    = f_vco_out / PLLP
USB48     = f_vco_out / PLLQ

f_pll_source is either HSE (an external crystal, commonly 8, 12, 16, or 25 MHz) or HSI (the internal 16 MHz RC oscillator). PLLM brings that down to a VCO input frequency. PLLN multiplies it back up inside the PLL’s voltage-controlled oscillator. PLLP divides the VCO output down to SYSCLK. PLLQ divides the same VCO output down again, separately, for USB OTG FS, SDIO, and RNG, which all need a clean 48 MHz.

Two dividers pull from the same VCO output because USB timing and CPU clock speed have nothing to do with each other. PLLP and PLLQ let you pick SYSCLK and USB48 independently, as long as both divide evenly from the one VCO frequency you picked with M and N.

The valid ranges (RM0090, cross-checked against the HAL asserts)

2 ≤ PLLM ≤ 63
50 ≤ PLLN ≤ 432          (192-432 on STM32F411xE)
PLLP ∈ {2, 4, 6, 8}
2 ≤ PLLQ ≤ 15

1 MHz ≤ f_vco_in ≤ 2 MHz   (2 MHz recommended, lowest jitter)
100 MHz ≤ f_vco_out ≤ 432 MHz

The VCO input range is tighter than people expect. RM0090 recommends landing exactly on 2 MHz to minimize PLL jitter; anything from 1 to 2 MHz is legal, but straying from 2 MHz trades jitter margin for divisor convenience. The VCO output range matters more in practice: pick PLLN too high for your PLLM and you silently violate 432 MHz, and CubeMX (or your own register math, if you’re doing this by hand) will accept the value without complaint unless you check it against the datasheet limit yourself.

STM32F7 (RM0410) uses the identical PLLCFGR layout and the identical M/N/P/Q ranges as F4. The only thing that changes is SYSCLK’s ceiling.

Worked example: 8 MHz HSE to 168 MHz

The most common F405/407 configuration, and the one that also lands USB exactly on 48 MHz:

PLLM = 4   → f_vco_in  = 8 MHz / 4   = 2 MHz     (recommended input)
PLLN = 168 → f_vco_out = 2 MHz × 168 = 336 MHz    (within 100-432 MHz)
PLLP = 2   → SYSCLK    = 336 MHz / 2 = 168 MHz    (F405/407/415/417 max)
PLLQ = 7   → USB48     = 336 MHz / 7 = 48 MHz     (exact)

Every field lands cleanly: VCO input at the recommended 2 MHz, VCO output well inside range, SYSCLK at the part’s ceiling, USB dead-on 48 MHz. This is why 8 MHz HSE with M=4 shows up in almost every STM32F4 board support package.

A 25 MHz HSE crystal (common on Nucleo boards, sourced from the on-board ST-LINK) hits the same 168 MHz target through a different path: PLLM = 25 gives f_vco_in = 1 MHz (valid, but not the 2 MHz recommendation, since no integer PLLM divides 25 MHz down to exactly 2 MHz), PLLN = 336 gives the same 336 MHz VCO output, PLLP = 2 and PLLQ = 7 give the same 168 MHz SYSCLK and 48 MHz USB. Different HSE, different M/N, identical VCO output, identical result. That’s the general pattern: many (M, N) pairs can reach the same VCO frequency, so the VCO output value, not the individual M or N, is what actually determines whether you’re inside the datasheet’s operating range.

When the VCO output hits the ceiling: STM32F7 at 216 MHz

F7 parts running at their 216 MHz ceiling have no headroom left in the VCO output range. With PLLM = 4 (2 MHz VCO input) and PLLP = 2, hitting 216 MHz SYSCLK requires PLLN = 216: f_vco_out = 2 MHz × 216 = 432 MHz, exactly the datasheet maximum. PLLQ = 9 gives 432 MHz / 9 = 48 MHz exactly, so USB still works.

Bump PLLN to 217 by mistake, an off-by-one that’s easy to introduce when you’re computing N by hand instead of round-tripping through the actual formula, and f_vco_out becomes 434 MHz: 2 MHz over the ceiling. Nothing in the register write stops you from doing this. The PLL will not lock reliably, or will lock at an out-of-spec frequency, and you get a MCU that behaves erratically or doesn’t boot, with no error flag pointing at the cause. Always compute f_vco_out for your chosen M/N pair and check it against 432 MHz before writing PLLCFGR, not after debugging a flaky board.

Edge cases and common mistakes

VCO output out of range. Pick PLLM too small relative to your HSE (say PLLM = 2 with an 8 MHz crystal) and f_vco_in jumps to 4 MHz, already outside 1-2 MHz. Multiply by any reasonable PLLN and f_vco_out blows past 432 MHz. The PLL either won’t lock or the reference manual’s behavior is undefined. Always start from the VCO input, get it into 1-2 MHz, then choose PLLN to land VCO output where you want it.

PLLP not in {2, 4, 6, 8}. Unlike PLLM, PLLN, and PLLQ, which are ordinary integer ranges, PLLP is a 2-bit field that only encodes those four specific values in hardware. There’s no way to divide by 3, 5, or 7 with PLLP. If your math wants a divider that isn’t in that set, adjust PLLN instead, since VCO output is continuously tunable through N while PLLP is not.

USB clock not exactly 48 MHz. USB OTG FS, SDIO, and RNG all clock off the same PLLQ tap and all require 48 MHz within a tight tolerance (the USB spec effectively demands it be exact, since there’s no separate trim). It’s easy to pick a PLLQ that gets SYSCLK-independent VCO output close to 48 MHz without landing on it exactly. At 336 MHz VCO output, PLLQ = 7 gives exactly 48 MHz; PLLQ = 6 gives 56 MHz, and PLLQ = 8 gives 42 MHz. Neither of those runs USB. If your target SYSCLK forces a VCO output that has no integer PLLQ landing on 48 MHz exactly (this happens: 360 MHz VCO output, the value that gives 180 MHz SYSCLK through PLLP = 2, has no integer divisor equal to 48 MHz, since 360/48 = 7.5), you cannot get USB from the main PLL at that operating point. F42x/43x parts running near 180 MHz commonly route USB through PLLSAI (a second, independent PLL) instead of PLLQ for exactly this reason.

Forgetting the family’s SYSCLK ceiling. The PLL math doesn’t know or care about your specific part’s absolute maximum frequency: it will happily compute a valid-looking VCO configuration that produces a SYSCLK your silicon isn’t rated for. STM32F405/407/415/417 top out at 168 MHz. F42x/43x/446/469/479 go to 180 MHz. F7 parts reach up to 216 MHz. Running above your part’s rated maximum is out of spec even if every individual PLLCFGR field is within its own valid range.

What this calculator does not model

This tool covers the classic single-main-PLL topology in STM32F4 and F7 (same PLLCFGR register, same field ranges). It does not model STM32H7, which adds separate pre-dividers (DIVM1/2/3), post-dividers (DIVP/Q/R per PLL), and fractional-N support across three independent PLLs, a materially different register layout. It also does not model STM32F1, which uses a much simpler prediv/mul scheme with no VCO stage at all (PLL output = PREDIV input × PLLMUL, no separate input/output frequency ranges to satisfy). STM32L4 and G4 share the conceptual M/N/P/Q idea but use different numeric ranges, a different VCO input range, and an additional PLLR divider not present on F4/F7; don’t reuse F4/F7 register values on an L4 or G4 part. Check the RCC chapter of your specific part’s reference manual before trusting any PLL configuration in production, regardless of which calculator produced it.

STM32 PLL / Clock Tree Calculator

Input

Result

Common HSE crystal configurations