ADC Resolution & ENOB Calculator

Calculate ideal ADC SNR, LSB size, and quantization noise from resolution and Vref, or derive ENOB and bits lost from a measured SINAD figure.

Parameters

Result

Ideal SNR

74.00 dB

6.02 × 12 + 1.76

LSB size

806 µV

Dynamic range

72.24 dB

Quantization noise RMS (LSB / √12)

233 µV

Ideal SNR & LSB by resolution (Vref = 3.3 V)

ResolutionLSBIdeal SNRDynamic range
8-bit12.9 mV49.92 dB48.16 dB
10-bit3.22 mV61.96 dB60.20 dB
12-bit806 µV74.00 dB72.24 dB
14-bit201 µV86.04 dB84.28 dB
16-bit50.4 µV98.08 dB96.32 dB
18-bit12.6 µV110.12 dB108.36 dB
20-bit3.15 µV122.16 dB120.40 dB
24-bit197 nV146.24 dB144.48 dB

Click a row to load that resolution. Real ADCs never reach the ideal SNR — see ENOB in Measured mode.

How it works

An ADC’s datasheet resolution (8-bit, 12-bit, 16-bit) is a count of output bits, not a measurement of accuracy. It tells you the LSB size:

LSB = Vref / 2^N

For a 12-bit ADC with a 3.3 V reference, LSB = 3.3 / 4096 = 805.7 µV. That’s the smallest voltage step the converter can represent — it says nothing about noise, linearity, or how many of those bits actually carry real signal information.

Deriving 6.02N + 1.76

Feed a full-scale sine wave into an otherwise perfect (noiseless) N-bit quantizer. The only error source is quantization: rounding each sample to the nearest LSB. That error is uniformly distributed between −LSB/2 and +LSB/2, so its RMS value is:

noise_rms = LSB / √12

A full-scale sine wave with peak amplitude Vref/2 has RMS power:

signal_rms = (Vref/2) / √2
signal_power = Vref² / 8

Quantization noise power is noise_power = LSB² / 12. Substitute LSB = Vref / 2^N:

SNR = 10 × log10(signal_power / noise_power)
    = 10 × log10((Vref²/8) / (Vref² / (12 × 2^2N)))
    = 10 × log10(1.5 × 2^2N)
    = 10 × log10(1.5) + 20N × log10(2)
    = 1.76 + 6.02N   (dB)

That’s the theoretical ceiling: the best SNR any N-bit converter can produce, assuming zero thermal noise, zero reference noise, zero DNL/INL error, and a full-scale sine input. Dynamic range (the ratio between the largest and smallest representable signal) is close but not identical — it drops the +1.76 dB sine-specific term and is approximately 6.02N dB.

SINAD and ENOB

Real converters never hit the ideal SNR. Thermal noise in the sample-and-hold, reference noise, comparator uncertainty, and harmonic distortion from the analog front end all eat into it. Run an FFT on the ADC output with a clean full-scale sine input and you get SINAD (signal-to-noise-and-distortion): the ratio of signal power to everything else in the spectrum, noise and harmonics both.

Solve the SNR equation for N using the measured SINAD instead of the ideal SNR, and you get ENOB — effective number of bits:

ENOB = (SINAD − 1.76) / 6.02

ENOB is always ≤ the nominal resolution N. The difference, N − ENOB, is how many bits of the register value are effectively noise rather than signal.

Worked example

12-bit ADC, Vref = 3.3 V.

Ideal SNR = 6.02 × 12 + 1.76 = 74.0 dB. LSB = 3.3 / 4096 = 805.7 µV. Quantization noise RMS = LSB / √12 = 232.6 µV.

Now suppose a bench FFT test on the actual silicon measures SINAD = 68 dB — this is an illustrative number, not a specific datasheet spec, so verify against your part’s actual characterization data before using it in a design decision.

ENOB = (68 − 1.76) / 6.02 = 11.0 bits
bits lost = 12 − 11.0 = 1.0 bit
effective LSB = 3.3 / 2^11.0 = 1.61 mV

One lost bit doesn’t sound like much, but it doubles the effective LSB. A sensor reading that should resolve to 0.8 mV now only resolves to 1.6 mV — halve your usable dynamic range before you’ve written a line of firmware.

Common use cases in embedded systems

nRF52 SAADC characterization. The SAADC on nRF52832/840 supports 8/10/12/14-bit modes. The 14-bit mode is oversampled internally and its ENOB is meaningfully below 14 — check the “SAADC electrical specification” table in the Nordic datasheet for the actual SINAD/ENOB at your gain and acquisition time settings before assuming you get all 14 bits of usable resolution.

STM32 ADC characterization. ST publishes ENOB figures in the “Electrical characteristics” chapter of each part’s datasheet, usually specified at a given clock frequency and sampling time. Faster sampling times reduce ENOB because the sample-and-hold capacitor has less time to settle — if you push SMPR to the minimum for higher throughput, re-check the ENOB spec at that setting.

Why datasheet ENOB is always less than nominal resolution. This isn’t a marketing gap or a defect — it’s physics. Every real ADC has thermal (kT/C) noise from the sample-and-hold capacitor, reference noise, and some level of DNL/INL error from the conversion architecture itself. A 16-bit sigma-delta ADC (ADS1115-class part) commonly specifies ENOB in the 15–15.5 range at its slowest data rate, and less at faster rates — check your specific part’s table, don’t assume.

Oversampling to recover effective bits. Averaging N independent, uncorrelated samples reduces the noise floor by √N, which works out to a gain of log2(N)/2 effective bits. 4× oversampling and averaging buys about 1 extra effective bit; 16× buys 2 bits; 64× buys 3 bits. This only helps for noise that’s genuinely random and dithers across the LSB threshold — averaging a static, quiet signal with no dither adds nothing, and it never fixes systematic (INL/DNL) error, only random noise.

Sensor front-end noise dominating at low signal levels. A photodiode transimpedance amplifier, a thermocouple amp, or a strain gauge bridge often has more input-referred noise than the ADC’s own quantization floor, especially at low signal amplitudes. In that case the ADC’s ENOB spec is irrelevant — the analog front end sets the real noise floor, and adding ADC resolution beyond that just digitizes more noise. Check the front-end’s input-referred noise density (nV/√Hz) against the ADC’s quantization noise RMS before spending money on a higher-resolution part.

Common mistakes

Assuming nominal resolution equals actual resolution. A “16-bit” ADC on a register value doesn’t mean 16 bits of real signal information. Always check the ENOB or SINAD spec at your actual operating conditions (clock speed, sample rate, reference source) before you design a system around a resolution requirement.

Ignoring input-referred noise from the analog front end. Op-amps, instrumentation amps, and sensor bridges all add noise before the signal reaches the ADC. If that noise exceeds the ADC’s own quantization noise, more ADC bits buy you nothing — the front end is the bottleneck. Compute or measure the front end’s noise and compare it against LSB / √12 for your target resolution.

Confusing dynamic range with SNR. Dynamic range (≈6.02N dB) describes the ratio between the largest and smallest representable signal — a resolution figure that doesn’t require a specific test signal. SNR and SINAD are noise measurements that only mean something relative to a defined signal amplitude, usually full-scale. Don’t quote a dynamic-range number as if it were a noise spec, and don’t quote SINAD without stating the signal level it was measured at.

Forgetting ENOB requires a full-scale test signal to be meaningful. SINAD — and therefore ENOB — is only comparable across parts and datasheets when measured with a full-scale sine input at a specified frequency and sample rate. A SINAD number measured with a small-amplitude signal looks much worse (lower SNR relative to a fixed noise floor) and isn’t the number in the datasheet’s headline spec. If you’re benchmarking your own hardware, drive the input to full scale before running the FFT.

Frequently asked questions

Why is my ADC's real ENOB lower than its nominal resolution? +

Nominal resolution only counts quantization error — it assumes a perfect, noiseless converter. Real ADCs add thermal noise, DNL/INL error, aperture jitter, and reference noise on top of that. A 12-bit SAR ADC on an MCU commonly measures 9.5–10.5 ENOB once you run an FFT on a full-scale sine input and compute SINAD. The gap between nominal resolution and ENOB is the converter's real-world noise floor, not a defect — check the datasheet's 'effective number of bits' or 'SINAD' table at your actual clock and sample rate.

Does oversampling actually recover the lost bits? +

Yes, within limits. Averaging N oversampled conversions reduces uncorrelated noise by √N, which is a gain of log2(N)/2 effective bits. Going from 12-bit to 14-bit-equivalent noise floor requires 4× oversampling (log2(4)/2 = 1 bit). It only works if the noise is uncorrelated sample-to-sample and dithered enough to toggle the LSB — averaging a static, noiseless signal doesn't add resolution, and it does nothing for INL/DNL error, which is systematic, not random.

What's the difference between SNR, SINAD, and dynamic range? +

SNR compares signal power to noise power only, excluding harmonics. SINAD (signal-to-noise-and-distortion) includes both noise and harmonic distortion, so it's always ≤ SNR and is what you should use to compute ENOB. Dynamic range is the ratio between the largest and smallest signals the converter can represent, roughly 6.02×N dB — it's a resolution figure, not a noise measurement, and doesn't require a full-scale input to define.

Why does the calculator warn that my SINAD is 'impossible'? +

The 6.02×N + 1.76 dB figure is the noise floor of a perfect quantizer with no other noise sources — it is the maximum SNR physically achievable at that resolution. A measured SINAD above that limit means one of the inputs is wrong: N doesn't match the ADC that produced the measurement, Vref doesn't match the test conditions, or the SINAD figure itself was computed incorrectly (e.g. from a non-full-scale input, which inflates the apparent SINAD).

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