Why does my I2S DAC output silence even though BCLK and WS look correct on a scope?

Check the slot width your codec expects versus the bit depth you're sending. Many DACs (WM8960, ES8388, CS4344-class parts) expect 16-bit or 24-bit audio inside a 32-bit slot, not a tightly packed 16-bit or 24-bit slot. If you clock BCLK for a 16-bit slot but the codec is configured for a 32-bit container, every sample lands in the wrong bit position and you get silence or noise. Check the codec's audio interface format table for the required word length / container width.

Do I need MCLK if BCLK and WS are already correct?

Depends on the part. A microcontroller acting as I2S transmitter never needs MCLK; BCLK and WS carry all the timing it needs. Many codec ICs do need MCLK because they use it to drive an internal PLL or sigma-delta modulator that's independent of the digital bus timing. Check your specific codec's datasheet — some parts (like the PCM5102) can derive a clock internally from BCLK alone in a no-MCLK mode, others require external MCLK at a specific ratio (typically 256×fs or 384×fs) to function at all.

Why can't I get exactly 44.1 kHz from my 12.288 MHz MCLK crystal?

12.288 MHz is 256×48000, part of the 48 kHz clock family. The 44.1 kHz family (44.1/88.2/176.4 kHz) needs a different base, 11.2896 MHz (256×44100). The two families don't share a clean common master clock. If your hardware only has a 12.288 MHz crystal, you need a fractional PLL (ESP32's APLL, STM32's PLLSAI) or a second crystal to hit 44.1 kHz-family rates accurately.

How does the nRF52 I2S peripheral generate BCLK without a classic prescaler register?

The nRF52 I2S peripheral derives a master clock (MCK) from HFCLK using CONFIG.MCKFREQ, then divides MCK by a ratio set in CONFIG.RATIO (32X through 512X) to get BCLK. You choose MCKFREQ and RATIO together so BCLK lands on fs × slot_width × channels for your target sample rate. See the I2S chapter of the nRF52832 or nRF52840 Product Specification for the exact register encoding.

I2S Bit Clock Calculator

Ratio	MCLK	MCLK / BCLK integer?
128×fs	6.144 MHz	yes
192×fs	9.216 MHz	yes
256×fsmost common	12.288 MHz	yes
384×fs	18.432 MHz	yes
512×fs	24.576 MHz	yes
768×fs	36.864 MHz	yes

What BCLK, WS, and MCLK actually are

I2S (and its close relatives, left-justified and TDM) move audio over three or four wires: a bit clock (BCLK, sometimes SCK), a word select line (WS, also called LRCLK), a serial data line (SD), and often a separate master clock (MCLK) that the transmitter doesn’t strictly need but most codecs do.

BCLK clocks one data bit per edge. WS marks channel boundaries: in the Philips I2S format, WS is low during the left channel and high during the right channel, and each channel’s MSB arrives one BCLK cycle after the WS edge. MCLK is a separate, usually higher-frequency clock that feeds a codec’s internal PLL or sigma-delta modulator. It has no fixed mathematical relationship to BCLK unless the same clock generator derives both.

The BCLK formula

BCLK = fs × slot_width × channels

fs is the sample rate. slot_width is how many bits are clocked out per channel per frame, not necessarily the same as the audio bit depth. channels is 2 for stereo I2S, or the slot count for TDM.

Derivation: every WS period (one full frame) carries channels slots, each slot_width bits wide, and BCLK produces exactly one bit per edge. So the number of BCLK edges per WS period is slot_width × channels. Since WS toggles once per sample period at rate fs, BCLK is that count times fs.

Worked example: 48 kHz, 16-bit, stereo, slot width equal to bit depth.

BCLK = 48000 × 16 × 2 = 1,536,000 Hz = 1.536 MHz
WS   = 48,000 Hz

Every WS period is 1/48000 s = 20.83 µs, during which 32 bits move across SD (16 left, 16 right) at 1.536 MHz.

Slot width vs. bit depth: the mismatch that breaks naive calculations

Bit depth is how many bits of actual audio resolution you have. Slot width is how many bits the protocol clocks out per channel, and codecs frequently pad it. A 16-bit or 24-bit stream is commonly carried in 32-bit slots (“I2S 32-bit container mode”), because a lot of codec silicon standardizes on a 32-bit frame regardless of the audio’s native resolution.

Same 48 kHz/16-bit/stereo audio, 32-bit slots instead of 16-bit:

BCLK = 48000 × 32 × 2 = 3,072,000 Hz = 3.072 MHz

Double the BCLK for identical audio data. Extra bits beyond the 16 that carry real samples are padded with zeros (or ignored on receive), but the clock still has to run at the container width. Datasheets for parts like the WM8960, ES8388, and CS4344 specify the required container width in their audio interface format table, usually under a heading like “word length” or “DSP/I2S timing.” If your DAC produces silence or garbled audio despite correct BCLK math, check whether it expects a 32-bit container for 16-bit data before suspecting anything else.

MCLK: a separate clock, not a derived one

Most I2S transmitters (a microcontroller acting as bus master) don’t need MCLK at all; BCLK and WS are sufficient to move data. Codecs are a different story. Many ADCs and DACs use MCLK to drive an internal PLL that generates the actual sampling clock, decoupled from the digital bus timing. Without MCLK, some codecs won’t produce a clean output, or won’t initialize at all.

MCLK is conventionally expressed as a multiple of fs: 128×, 192×, 256×, 384×, 512×, or 768×fs. 256×fs is the most widely supported ratio across cheap I2S DAC boards; check your specific part’s datasheet before assuming it. At 48 kHz, 256×fs = 12.288 MHz, which is why 12.288 MHz crystals are a standard stock item at electronics distributors. At 44.1 kHz, 256×fs = 11.2896 MHz, the other common audio crystal value. The 44.1 kHz family (44.1, 88.2, 176.4 kHz) and the 48 kHz family (48, 96, 192 kHz) don’t share a clean common master clock, which is why professional audio interfaces often carry two separate crystal oscillators.

Some codecs also require MCLK to divide evenly into BCLK, or specify a fixed MCLK/BCLK ratio for their internal clock recovery. The reference table on this calculator flags which MCLK ratios divide evenly by the computed BCLK for your current slot width and channel count. If none divide evenly and your codec’s datasheet requires it, adjusting slot width (e.g. 24-bit vs 32-bit container) is usually the fix, since it changes BCLK without changing the audio data itself.

MCU-specific clock generation

nRF52 I2S peripheral derives everything from HFCLK (32 MHz on the internal peripheral bus after PLL). CONFIG.MCKFREQ sets the MCK/HFCLK ratio, and CONFIG.RATIO (one of NRF_I2S_RATIO_32X through NRF_I2S_RATIO_512X) sets BCLK = MCK / RATIO. You pick MCKFREQ and RATIO so that the resulting BCLK matches fs × slot_width × channels for your target sample rate; the nRF52 Product Specification’s I2S chapter has the exact register encoding.

STM32 SAI peripheral has its own PLL (PLLSAI or PLLI2S depending on family) to generate a master clock independent of the main system clock tree, then an internal divider (MCKDIV) brings that down to BCLK/FS_CK. This lets an STM32 hit arbitrary audio sample rates without disturbing the CPU or peripheral clock tree.

ESP32 I2S uses the APLL (Audio PLL), a fractional-N synthesizer that can produce an accurate MCLK for essentially any sample rate. The ESP-IDF driver computes the APLL configuration automatically when you set mclk_multiple in i2s_std_config_t.

When the simple formula breaks down

Left-justified vs. I2S vs. DSP/PCM mode. All three modes can share the same BCLK/WS math, but WS timing differs: I2S has WS transition one BCLK before the MSB, left-justified aligns WS exactly with the MSB, and DSP/PCM mode uses a single-cycle WS pulse rather than a 50% duty square wave. Getting BCLK right doesn’t guarantee correct audio if the mode doesn’t match what the codec expects.

TDM beyond 2 channels. Digital microphone arrays commonly run 4 or 8 channels over a shared BCLK/WS/SD, with each mic’s ASIC address hardwired to a specific slot. The BCLK formula still holds (channels becomes the slot count), but WS often becomes a single-cycle frame sync rather than a 50% square wave, and slot ordering must match the physical mic wiring, not just the clock math.

Fixed MCLK crystals with arbitrary sample rates. If your board has a fixed MCLK crystal (e.g. 12.288 MHz for 48 kHz-family rates) and you need 44.1 kHz, no integer ratio gets you there cleanly. You need either a second crystal, a fractional PLL (APLL on ESP32, PLLSAI on STM32), or an external clock generator IC. Don’t assume a codec can be run from an MCLK that isn’t a clean multiple of the target fs and expect accurate sample timing.

I2S Bit Clock Calculator

Parameters

Result

Common MCLK ratios (codec master clock)